Choice of Memory Organizations

– SN74V3640 – 1024 × 36 Bit

– SN74V3650 – 2048 × 36 Bit

– SN74V3660 – 4096 × 36 Bit

– SN74V3670 – 8192 × 36 Bit

– SN74V3680 – 16384 × 36 Bit

– SN74V3690 – 32768 × 36 Bit

166-MHz Operation (6-ns Read/Write Cycle

Time)

User-Selectable Input- and Output-Port Bus

Sizing

– ×36 in to ×36 out

– ×36 in to ×18 out

– ×36 in to ×9 out

– ×18 in to ×36 out

– ×9 in to ×36 out

Big-Endian/Little-Endian User-Selectable

Byte Representation

5-V-Tolerant Inputs

Fixed, Low, First-Word Latency

Zero-Latency Retransmit

Master Reset Clears Entire FIFO

Partial Reset Clears Data, But Retains

Programmable Settings

Empty, Full, and Half-Full Flags Signal FIFO

Status

Programmable Almost-Empty and

Almost-Full Flags; Each Flag Can Default to

One of Eight Preselected Offsets

Selectable Synchronous/Asynchronous

Timing Modes for Almost-Empty and

Almost-Full Flags

Program Programmable Flags by Either

Serial or Parallel Means

Select Standard Timing (Using EF and FF

Flags) or First-Word Fall-Through (FWFT)

Timing (Using OR and IR Flags)

Output Enable Puts Data Outputs in

High-Impedance State

Easily Expandable in Depth and Width

Independent Read and Write Clocks Permit

Reading and Writing Simultaneously

High-Performance Submicron CMOS

Technology

Available in 128-Pin Thin Quad Flat Pack

(TQFP)

description

The SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 are exceptionally

deep, high-speed CMOS, first-in first-out (FIFO) memories, with clocked read and write controls and a flexible

bus-matching ×36/×18/×9 data flow. These FIFOs offer several key user benefits:

Flexible ×36/×18/×9 bus matching on both read and write ports

The period required by the retransmit operation is fixed and short.

The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can

be read, is fixed and short.

High-density offerings up to 1 Mbit

Bus-matching synchronous FIFOs are particularly appropriate for network, video, signal processing,

telecommunications, data communications, and other applications that need to buffer large amounts of data

and match buses of unequal sizes.

Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume 36-bit, 18-bit, or

9-bit width, as determined by the state of external control pins’ input width (IW), output width (OW), and bus

matching (BM) during the master-reset cycle.