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SN74LVTH16374DLR.Z中文资料

厂家型号

SN74LVTH16374DLR.Z

文件大小

1014.95Kbytes

页面数量

19

功能描述

3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

数据手册

下载地址一下载地址二到原厂下载

生产厂商

TI2

SN74LVTH16374DLR.Z数据手册规格书PDF详情

FEATURES

· Members of the Texas Instruments Widebus™

Family

· State-of-the-Art Advanced BiCMOS

Technology (ABT) Design for 3.3-V Operation

and Low Static-Power Dissipation

· Support Mixed-Mode Signal Operation (5-V

Input and Output Voltages With 3.3-V VCC)

· Support Unregulated Battery Operation Down

to 2.7 V

· Typical VOLP (Output Ground Bounce) <0.8 V at

VCC = 3.3 V, TA = 25°C

· Ioff and Power-Up 3-State Support Hot Insertion

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· Distributed VCC and GND Pins Minimize

High-Speed Switching Noise

· Flow-Through Architecture Optimizes PCB

Layout

· Latch-Up Performance Exceeds 500 mA Per

JESD 17

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

DESCRIPTION/ORDERING INFORMATION

The 'LVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for low-voltage

(3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These

devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working

registers.

These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock

(CLK), the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or

low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the

bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines

without need for interface or pullup components.

OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors

with the bus-hold circuitry is not recommended.

更新时间:2025-10-18 15:14:00
供应商 型号 品牌 批号 封装 库存 备注 价格
TI(德州仪器)
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509
TI/德州仪器
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7600
TI/德州仪器
24+
SSOP-48_300mil
6000
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TI/德州仪器
2022+
SSOP-48_300mil
7600
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TI/德州仪器
SSOP-48_300mil
6000
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TI/德州仪器
21+
SSOP-48_300mil
26880
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TI/德州仪器
23+
SSOP-48_300mil
8080
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TI/德州仪器
25+
SSOP-48_300mil
9980
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TI/德州仪器
25
SSOP-48_300mil
6000
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TI/德州仪器
2023+
SSOP-48_300mil
6000
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