位置:SN74LVTH126PW.B > SN74LVTH126PW.B详情

SN74LVTH126PW.B中文资料

厂家型号

SN74LVTH126PW.B

文件大小

781.66Kbytes

页面数量

23

功能描述

3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS

数据手册

下载地址一下载地址二到原厂下载

生产厂商

TI2

SN74LVTH126PW.B数据手册规格书PDF详情

Support Mixed-Mode Signal Operation (5-V

Input and Output Voltages With 3.3-V VCC)

Support Unregulated Battery Operation

Down to 2.7 V

Typical VOLP (Output Ground Bounce)

<0.8 V at VCC = 3.3 V, TA = 25°C

Ioff and Power-Up 3-State Support Hot

Insertion

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

description/ordering information

These bus buffers are designed specifically for

low-voltage (3.3-V) VCC operation, but with the

capability to provide a TTL interface to a 5-V

system environment.

The ’LVTH126 devices feature independent line

drivers with 3-state outputs. Each output is in the

high-impedance state when the associated

output-enable (OE) input is low.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors

with the bus-hold circuitry is not recommended.

更新时间:2025-10-6 15:14:00
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