State-of-the-Art Advanced BiCMOS

Technology (ABT) Design for 3.3-V

Operation and Low Static Power

Dissipation

Support Mixed-Mode Signal Operation (5-V

Input and Output Voltages With 3.3-V VCC)

Support Unregulated Battery Operation

Down to 2.7 V

Typical VOLP (Output Ground Bounce)

0.8 V at VCC = 3.3 V, TA = 25°C

ESD Protection Exceeds 2000 V Per

MIL-STD-883C, Method 3015; Exceeds

200 V Using Machine Model

C = 200 pF, R = 0)

Latch-Up Performance Exceeds 500 mA

Per JEDEC Standard JESD-17

Bus-Hold Data Inputs Eliminate the Need

for External Pullup Resistors

Support Live Insertion

Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

DB), and Thin Shrink Small-Outline (PW)

Packages, Ceramic Chip Carriers (FK), and

Ceramic (JT) DIPs