Members of the Texas Instruments

SCOPE E Family of Testability Products

Members of the Texas Instruments

WidebusE Family

State-of-the-Art 3.3-V ABT Design Supports

Mixed-Mode Signal Operation (5-V Input

and Output Voltages With 3.3-V VCC)

Support Unregulated Battery Operation

Down to 2.7 V

UBT E (Universal Bus Transceiver)

Combines D-Type Latches and D-Type

Flip-Flops for Operation in Transparent,

Latched, or Clocked Mode

B-Port Outputs of ’LVT182512 Devices

Have Equivalent 25-W Series Resistors, So

No External Resistors Are Required

Compatible With the IEEE Std 1149.1-1990

(JTAG) Test Access Port and

Boundary-Scan Architecture

SCOPE E Instruction Set

– IEEE Std 1149.1-1990 Required

Instructions and Optional CLAMP and

HIGHZ

– Parallel-Signature Analysis at Inputs

– Pseudo-Random Pattern Generation

From Outputs

– Sample Inputs/Toggle Outputs

– Binary Count From Outputs

– Device Identification

– Even-Parity Opcodes

Package Options Include 64-Pin Plastic

Thin Shrink Small Outline (DGG) and 64-Pin

Ceramic Dual Flat (HKC) Packages Using

0.5-mm Center-to-Center Spacings

description

The ’LVT18512 and ’LVT182512 scan test devices with 18-bit universal bus transceivers are members of the

Texas Instruments SCOPEE testability integrated-circuit family. This family of devices supports IEEE Std

1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test

circuitry is accomplished via the 4-wire test access port (TAP) interface.

Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the

capability to provide a TTL interface to a 5-V system environment.

In the normal mode, these devices are 18-bit universal bus transceivers that combine D-type latches and D-type

flip-flops to allow data flow in transparent, latched, or clocked modes. They can be used either as two 9-bit

transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples

of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP

in the normal mode does not affect the functional operation of the SCOPEE universal bus transceivers.

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),

and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when

LEAB is high. When LEAB is low, the A data is latched while CLKAB is held at a static low or high logic level.

Otherwise, if LEAB is low, A data is stored on a low-to-high transition of CLKAB. When OEAB is low, the B

outputs are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is similar

to A-to-B data flow but uses the OEBA, LEBA, and CLKBA inputs.

In the test mode, the normal operation of the SCOPEE universal bus transceivers is inhibited, and the test

circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry

performs boundary-scan test operations according to the protocol described in IEEE Std 1149.1-1990.

Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI),

test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs

other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern

generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

The B-port outputs of ’LVT182512, which are designed to source or sink up to 12 mA, include equivalent 25-W

series resistors to reduce overshoot and undershoot.

The SN54LVT18512 and SN54LVT182512 are characterized for operation over the full military temperature

range of –55°C to 125°C. The SN74LVT18512 and SN74LVT182512 are characterized for operation from

–40°C to 85°C.