State-of-the-Art Advanced BiCMOS

Technology (ABT) Design for 3.3-V

Operation and Low-Static Power

Dissipation

Members of the Texas Instruments

WidebusE Family

Support Mixed-Mode Signal Operation (5-V

Input and Output Voltages With 3.3-V VCC)

Support Unregulated Battery Operation

Down to 2.7 V

UBTE (Universal Bus Transceiver)

Combines D-Type Latches and D-Type

Flip-Flops for Operation in Transparent,

Latched, or Clocked Mode

Typical VOLP (Output Ground Bounce)

< 0.8 V at VCC = 3.3 V, TA = 25°C

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model

(C = 200 pF, R = 0)

Latch-Up Performance Exceeds 500 mA

Per JEDEC Standard JESD-17

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

Support Live Insertion

Distributed VCC and GND Pin Configuration

Minimizes High-Speed Switching Noise

Flow-Through Architecture Optimizes

PCB Layout

Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages and 380-mil

Fine-Pitch Ceramic Flat (WD) Package

Using 25-mil Center-to-Center Spacings

description

The ’LVT16501 are 18-bit universal bus transceivers designed for low-voltage (3.3-V) VCC operation, but with

the capability to provide a TTL interface to a 5-V system environment.

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),

and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when

LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is

low, the A-bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high,

the outputs are active. When OEAB is low, the outputs are in the high-impedance state.