位置:SN74LVCE161284 > SN74LVCE161284详情

SN74LVCE161284中文资料

厂家型号

SN74LVCE161284

文件大小

470.41Kbytes

页面数量

18

功能描述

19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP

接口 - 专用 19-Bit IEEE 1284 Translation Xcvr

数据手册

原厂下载下载地址一下载地址二到原厂下载

生产厂商

TI2

SN74LVCE161284数据手册规格书PDF详情

FEATURES

· Auto-Power-Up Feature Prevents Printer

Errors When Printer Is Turned On, But No

Valid Signal Is at A9–A13 Pins

· 1.4-kW Pullup Resistors Integrated on All

Open-Drain Outputs Eliminate the Need for

Discrete Resistors

· Designed for IEEE Std 1284-I (Level-1 Type)

and IEEE Std 1284-II (Level-2 Type) Electrical

Specifications

· Flow-Through Architecture Optimizes PCB

Layout

· Ioff and Power-Up 3-State Support Hot

Insertion

· Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

· ESD Protection

– ±4 kV – Human-Body Model

– ±8 kV – IEC 61000-4-2, Contact Discharge

(Connector Pins)

– ±15 kV – IEC 61000-4-2, Air-Gap Discharge

(Connector Pins)

– ±15 kV – Human-Body Model

(Connector Pins)

DESCRIPTION/ORDERING INFORMATION

The SN74LVCE161284 is designed for 3-V to 3.6-V VCC operation. This device provides asynchronous two-way

communication between data buses. The control-function implementation minimizes external timing

requirements.

This device has eight bidirectional bits; data can flow in the A-to-B direction when the direction-control input (DIR)

is high and in the B-to-A direction when DIR is low. This device also has five drivers that drive the cable side and

four receivers. The SN74LVCE161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive

the PERI LOGIC line.

The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a

totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements

as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface

specifications. Except for HOST LOGIC IN and peripheral logic out (PERI LOGIC OUT), all cable-side pins have

a 1.4-kW integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low

state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low.

The device has two supply voltages. VCC is designed for 3-V to 3.6-V operation. VCC CABLE supplies the inputs

and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even

when VCC CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.

The Y outputs (Y9–Y13) stay in the high state after power on until an associated input (A9–A13) goes high.

When an associated input goes high, all Y outputs are activated, and noninverting signals of the associated

inputs are driven through Y outputs. This special feature prevents printer-system errors caused by deasserting

the BUSY signal in the cable at power on.

SN74LVCE161284产品属性

  • 类型

    描述

  • 型号

    SN74LVCE161284

  • 功能描述

    接口 - 专用 19-Bit IEEE 1284 Translation Xcvr

  • RoHS

  • 制造商

    Texas Instruments

  • 产品类型

    1080p60 Image Sensor Receiver

  • 工作电源电压

    1.8 V

  • 电源电流

    89 mA

  • 最大工作温度

    + 85 C

  • 安装风格

    SMD/SMT

  • 封装/箱体

    BGA-59

更新时间:2025-10-16 15:08:00
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SN74LVCE161284VR 价格

参考价格:¥10.2735

型号:SN74LVCE161284VR 品牌:TI 备注:这里有SN74LVCE161284多少钱,2025年最近7天走势,今日出价,今日竞价,SN74LVCE161284批发/采购报价,SN74LVCE161284行情走势销售排排榜,SN74LVCE161284报价。