1 Features

• Wide operating range of 1.65V to 5.5V

• 5.5V tolerant input pins

• Single-supply voltage translator (refer to LVxT

Enhanced Input Voltage):

– Up translation:

• 1.2V to 1.8V

• 1.5V to 2.5V

• 1.8V to 3.3V

• 3.3V to 5.0V

– Down translation:

• 5.0V, 3.3V, 2.5V to 1.8V

• 5.0V, 3.3V to 2.5V

• 5.0V to 3.3V

• Up to 150Mbps with 5V or 3.3V VCC

• Supports standard function pinout

• Latch-up performance exceeds 250mA

per JESD 17

• Supports defense and aerospace applications:

– Controlled baseline

– One assembly and test site

– One fabrication site

– Extended product life cycle

– Product traceability

2 Applications

• Enable or disable a digital signal

• Controlling an indicator LED

• Translation between communication modules and

system controllers

3 Description

The SN74LV8T595-EP device contains an 8-bit,

serial-in, parallel-out shift register that feeds an 8-

bit D-type storage register. The storage register has

parallel 3-state outputs. Separate clocks are provided

for both the shift and storage register. The shift

register has a direct overriding clear ( SRCLR) input,

serial (SER) input, and a serial output (QH') for

cascading. When the output-enable ( OE) input is

high, the outputs are in a high-impedance state.

Internal register data is not impacted by the operation

of the OE input. The output level is referenced to the

supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V,

and 5V CMOS levels.

The input is designed with a lower threshold circuit to

support up translation for lower voltage CMOS inputs

(for example, 1.2V input to 1.8V output or 1.8V input

to 3.3V output). In addition, the 5V tolerant input pins

enable down translation (for example, 3.3V to 2.5V

output).