FEATURES

· Inputs Are TTL-Voltage Compatible

· 4.5-V to 5.5-V V CC Operation

· Typical tpd of 5.1 ns at 5 V

· Typical V OLP (Output Ground Bounce)

<0.8 V at VCC = 5 V, TA = 25°C

· Typical V OHV (Output VOH Undershoot)

>2.3 V at VCC = 5 V, TA = 25°C

· Supports Mixed-Mode Voltage Operation on

All Ports

· Ioff Supports Partial-Power-Down Mode

Operation

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

The SN74LV373AT is an octal transparent D-type latch. While the latch-enable (LE) input is high, the Q outputs

follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D

inputs.