Qualified for Automotive Applications

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Targeted Specifically for High-Speed

Memory Decoders and Data-Transmission

Systems

2-V to 6-V VCC Operation

Outputs Can Drive Up To 10 LSTTL Loads

Low Power Consumption, 80-μA Max ICC

Typical tpd = 15 ns

4-mA Output Drive at 5 V

Low Input Current of 1 μA Max

Incorporate Three Enable Inputs to Simplify

Cascading and/or Data Reception

description/ordering information

The SN74HC138 is designed to be used in high-performance memory-decoding or data-routing applications

requiring very short propagation delay times. In high-performance memory systems, this decoder can be used

to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable

circuit, the delay times of this decoder and the enable time of the memory usually are less than the typical access

time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The conditions at the binary-select inputs at the three enable inputs select one of eight output lines. Two

active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.

A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one

inverter. An enable input can be used as a data input for demultiplexing applications.