FEATURES

· TI-OPC™ Circuitry Limits Ringing on

Unevenly Loaded Backplanes

· OEC™ Circuitry Improves Signal Integrity and

Reduces Electromagnetic Interference

· Bidirectional Interface Between GTLP Signal

Levels and LVTTL Logic Levels

· Split LVTTL Port Provides a Feedback Path

for Control and Diagnostics Monitoring

· LVTTL Interfaces Are 5-V Tolerant

· High-Drive GTLP Outputs (100 mA)

· LVTTL Outputs (–24 mA/24 mA)

· Variable Edge-Rate Control (ERC) Input

Selects GTLP Rise and Fall Times for Optimal

Data-Transfer Rate and Signal Integrity in

Distributed Loads

· Ioff, Power-Up 3-State, and BIAS VCC Support

Live Insertion

· Polarity Control Selects True or

Complementary Outputs

· Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)