FEATURES

· Operates as a GTL–/GTL/GTL+ to LVTTL or

LVTTL to GTL–/GTL/GTL+ Translator

· Series Termination on TTL Output of 30 W

· Latch-Up Testing Done to JEDEC Standard

JESD 78

· ESD Performance Tested Per JESD 22

– 2000-V Human-Body Model

(A114-B, Class II)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

The SN74GTL2107 is a 12-bit translator that interfaces between the 3.3-V LVTTL chip set I/O and the Xeon™

processor GTL–/GTL/GTL+ I/O. The device is designed for platform health management in dual-processor

applications.