1 Features

• Fully configurable dual-rail design allows each port

to operate with a power supply range from 0.65 V

to 3.6 V

• Operating temperature from –40°C to +125°C

• Independent direction control pins to allow

configurable up and down translation

• Glitch-free power supply sequencing

• Up to 310 Mbps support when translating from 1.8

V to 3.3 V

• VCC isolation feature

– If either VCC input is below 100 mV, all

I/Os outputs are disabled and become highimpedance

• Ioff supports partial-power-down mode operation

• Compatible with AVC family level shifters

• Latch-up performance exceeds 100 mA per JESD

78, Class II

• ESD protection exceeds JESD 22

– 8000-V human-body model

– 1000-V charged-device model

2 Applications

• Enterprise and communications

• Industrial

• Personal electronics

• Wireless infrastructure

• Building automation

• Point of sale

3 Description

The SN74AXC4T774 is a four-bit non-inverting bus

transceiver that uses two individually configurable

power-supply rails. The device is operational with both

VCCA and VCCB supplies as low as 0.65 V. The A port

is designed to track VCCA, which accepts any supply

voltage from 0.65 V to 3.6 V. The B port is designed

to track VCCB, which also accepts any supply voltage

from 0.65 V to 3.6 V. Additionally the SN74AXC4T774

is compatible with a single-supply system.

The SN74AXC4T774 device is designed for

asynchronous communication between data buses.

The device transmits data from the A bus to the B

bus or from the B bus to the A bus, depending on

the logic level of the direction-control inputs (DIRx).

The output-enable input (OE) is used to disable the

outputs so the buses are effectively isolated. The

SN74AXC4T774 device is designed so the control

pins (DIRx and OE) are referenced to VCCA.

To put the level shifter I/Os in the high-impedance

state during power up or power down, tie the OE pin

to VCCA through a pullup resistor.

This device is fully specified for partial-power-down

applications using the Ioff current. The Ioff protection

circuitry is designed so that no excessive current is

drawn from or to an input, output, or combined I/O

that is biased to a specific voltage while the device is

powered down.

The VCC isolation feature is designed so that if either

VCCA or VCCB is less than 100 mV, both I/O ports

are set to the high-impedance state by disabling their

outputs.

Glitch-free power supply sequencing allows either

supply rail to be powered on or off in any order while

providing robust power sequencing performance.