1 Features

• Latch-up performance exceeds 100 mA per JESD

78, Class II

• ESD protection exceeds JESD 22:

– 8000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

• Control inputs VIH/VIL levels are referenced to

VCCA voltage

• VCC isolation feature – if either VCC input is at

GND, all I/O ports are in the high-impedance state

• Ioff supports partial power-down mode operation

• Fully configurable dual-rail design allows each

port to operate over the full 1.4-V to 3.6-V powersupply

range

• I/Os are 4.6-V tolerant

• Maximum data rates:

– 170Mbps (VCCA < 1.8 V or VCCB < 1.8 V)

– 320Mbps (VCCA ≥ 1.8 V and VCCB ≥ 1.8 V)

2 Applications

• Personal electronic

• Industrial

• Enterprise

• Telecom

3 Description

This 8-bit noninverting bus transceiver uses two

separate configurable power-supply rails. The

SN74AVC8T245 is optimized to operate with VCCA/

VCCB set at 1.4 V to 3.6 V. The device is operational

with VCCA and VCCB as low as 1.2 V. The A port

is designed to track VCCA. VCCA accepts any supply

voltage from 1.2 V to 3.6 V. The B port is designed

to track VCCB. VCCB accepts any supply voltage from

1.2 V to 3.6 V. This allows for universal low-voltage

bidirectional translation between any of the 1.2-V, 1.5-

V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVC8T245 is designed for asynchronous

communication between data buses. The device

transmits data from the A bus to the B bus or from

the B bus to the A bus, depending on the logic level

at the direction-control (DIR) input. The output-enable

(OE) input can be used to disable the outputs so the

buses are effectively isolated.

The SN74AVC8T245 is designed so that the control

pins (DIR and OE) are supplied by VCCA.

The SN74AVC8T245 is compatible with a singlesupply

system and can be replaced later with a '245

function, with minimal printed circuit board redesign.

This device is fully specified for partial-power-down

applications using Ioff. The Ioff circuitry disables the

outputs, thus preventing damaging current backflow

through the device when it is powered down.

The VCC isolation feature allows both ports to be in

the high-impedance state when either VCC input is at

GND.

To put the device into the high-impedance state during

power up or power down, tie OE to VCC through a

pullup resistor; the current-sinking capability of the

driver determines the minimum value of the resistor.