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SN74AUP2G34DSFR.B中文资料

厂家型号

SN74AUP2G34DSFR.B

文件大小

1564.95Kbytes

页面数量

25

功能描述

LOW-POWER DUAL BUFFER GATE

数据手册

下载地址一下载地址二到原厂下载

生产厂商

TI2

SN74AUP2G34DSFR.B数据手册规格书PDF详情

1FEATURES

• Available in the Texas Instruments NanoStar™

Package

• Low Static-Power Consumption:

ICC = 0.9 mA Max

• Low Dynamic-Power Consumption:

Cpd = 4.3 pF Typ at 3.3 V

• Low Input Capacitance: Ci = 1.5 pF Typ

• Low Noise: Overshoot and Undershoot

<10% of VCC

• Ioff Supports Partial-Power-Down Mode

Operation

• Wide Operating VCC Range of 0.8 V to 3.6 V

• Optimized for 3.3-V Operation

• 3.6-V I/O Tolerant to Support Mixed-Mode

Signal Operation

• tpd = 4.3 ns Max at 3.3 V

• Suitable for Point-to-Point Applications

• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• ESD Performance Tested Per JESD 22

– 2000-V Human-Body Model

(A114-B, Class II)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable

applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range

of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal

integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).

更新时间:2026-2-15 15:13:00
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