1FEATURES

• Available in the Texas Instruments NanoStar™

Package

• Low Static-Power Consumption

(ICC = 0.9 mA Maximum)

• Low Dynamic-Power Consumption

(Cpd = 4.2 pF Typ at 3.3 V)

• Low Input Capacitance (Ci = 1.5 pF Typical)

• Low Noise – Overshoot and Undershoot

<10% of VCC

• Ioff Supports Partial-Power-Down Mode

Operation

• Wide Operating VCC Range of 0.8 V to 3.6 V

• Optimized for 3.3-V Operation

• 3.6-V I/O Tolerant to Support Mixed-Mode

Signal Operation

• tpd = 4.7 ns Maximum at 3.3 V

• Suitable for Point-to-Point Applications

• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• ESD Performance Tested Per JESD 22

– 2000-V Human-Body Model

(A114-B, Class II)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable

applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range

of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal

integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).

The SN74AUP2G240 is designed specifically to improve the performance and density of 3-state memory address

drivers, clock drivers, and bus-oriented receivers and transmitters.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the

package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.