Member of the Texas Instruments

Widebus Family

UBT  Transceiver Combines D-Type

Latches and D-Type Flip-Flops for

Operation in Transparent, Latched, or

Clocked Mode

Operates From 1.65 V to 3.6 V

Max tpd of 4.4 ns at 3.3 V

±24-mA Output Drive at 3.3 V

Simultaneously Generates and Checks

Parity

Option to Select Generate Parity and Check

or Feed-Through Data/Parity in A-to-B or

B-to-A Directions

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

Latch-Up Performance Exceeds 250 mA Per

JESD 17

ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

description/ordering information

This 18-bit (dual-octal) noninverting registered

transceiver is designed for 1.65-V to 3.6-V VCC

operation.

The SN74ALVCH16901 is a dual 9-bit to dual 9-bit

parity transceiver with registers. The device can

operate as a feed-through transceiver or it can

generate/check parity from the two 8-bit data

buses in either direction.

The SN74ALVCH16901 features independent

clock (CLKAB or CLKBA), latch-enable (LEAB or

LEBA), and dual 9-bit clock-enable (CLKENAB or CLKENBA) inputs. It also provides parity-enable (SEL) and

parity-select (ODD/EVEN) inputs and separate error-signal (ERRA or ERRB) outputs for checking parity. The

direction of data flow is controlled by OEAB and OEBA. When SEL is low, the parity functions are enabled. When

SEL is high, the parity functions are disabled, and the device acts as an 18-bit registered transceiver.