1 Features

• Operating range 2V to 5.5V VCC

• Contain eight flip-flops with single-rail outputs

• Direct clear input

• Individual data input to each flip-flop

• Latch-up performance exceeds 250mA per JESD

17

• ESD protection exceeds JESD 22

– 2000V human-body model (A114-A)

– 1000V charged-device model (C101)

• On products compliant to MIL-PRF-38535,

All parameters are tested unless otherwise noted.

On all other products, production processing does

not necessarily include testing of all parameters.

2 Applications

• Buffers and Storage Registers

• Shift Registers

• Pattern Generators

• Servers

• PCs and Notebooks

• Network Switches

• Memory Systems

• Databases

3 Description

These devices are positive-edge-triggered D-type

flip-flops with a direct clear ( CLR) input.

Information at the data (D) inputs meeting the setup

time requirements is transferred to the Q outputs on

the positive-going edge of the clock (CLK) pulse.

Clock triggering occurs at a particular voltage level

and is not directly related to the transition time of the

positive-going pulse. When CLK is at either the high

or low level, the D input has no effect at the output.