Members of the Texas Instruments

WidebusE Family

EPICE (Enhanced-Performance Implanted

CMOS) Process

Operating Range 2-V to 5.5-V VCC

Distributed VCC and GND Pins Minimize

High-Speed Switching Noise

Flow-Through Architecture Optimizes PCB

Layout

Latch-Up Performance Exceeds 250 mA Per

JESD 17

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015

Package Options Include Plastic Shrink

Small-Outline (DL), Thin Shrink

Small-Outline (DGG), and Thin Very

Small-Outline (DGV) Packages and 380-mil

Fine-Pitch Ceramic Flat (WD) Package

Using 25-mil Center-to-Center Spacings

description

These 16-bit buffers and bus drivers provide a

high-performance bus interface for wide data

paths.

The 3-state control gate is a 2-input AND gate with

active-low inputs so that if either output-enable

(OE1 or OE2) input is high, all corresponding

outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54AHC16540 is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74AHC16540 is characterized for operation from –40°C to 85°C.