Controlled Baseline

− One Assembly/Test Site, One Fabrication

Site

Extended Temperature Performance of

−55°C to 125°C

Enhanced Diminishing Manufacturing

Sources (DMS) Support

Enhanced Product-Change Notification

Qualification Pedigree†

4.5-V to 5.5-V VCC Operation

Inputs Accept Voltages to 5.5 V

Max tpd of 10.5 ns at 5 V

Inputs Are TTL-Voltage Compatible

description/ordering information

The SN74ACT74-EP is a dual positive-edge-triggered D-type flip-flop.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the

other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time

requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs

at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,

data at D can be changed without affecting the levels at the outputs.