State-of-the-Art EPIC-IIBE BiCMOS Design

Significantly Reduces Power Dissipation

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Latch-Up Performance Exceeds 500 mA Per

JEDEC Standard JESD-17

Typical VOLP (Output Ground Bounce) < 1 V

at VCC = 5 V, TA = 25°C

High-Drive Outputs (–32-mA IOH,

64-mA IOL)

Parity Error Flag With Parity

Generator/Checker

Register for Storage of the Parity Error Flag

Package Options Include Plastic

Small-Outline (DW) Packages, Ceramic

Chip Carriers (FK), and Plastic (NT) and

Ceramic (JT) DIPs

description

The ’ABT833 8-bit to 9-bit parity transceivers are

designed for communication between data buses.

When data is transmitted from the A bus to the

B bus, a parity bit is generated. When data is

transmitted from the B bus to the A bus with its

corresponding parity bit, the open-collector

parity-error (ERR) output indicates whether or not

an error in the B data has occurred. The

output-enable (OEA and OEB) inputs can be used

to disable the device so that the buses are

effectively isolated. The ’ABT833 provide true

data at their outputs.

A 9-bit parity generator/checker generates a

parity-odd (PARITY) output and monitors the

parity of the I/O ports with the ERR flag. ERR is

clocked into the register on the rising edge of the

clock (CLK) input. The error flag register is cleared

with a low pulse on the clear (CLR) input. When

both OEA and OEB are low, data is transferred

from the A bus to the B bus and inverted parity is

generated. Inverted parity is a forced error

condition that gives the designer more system

diagnostic capability.