Output Ports Have Equivalent 25-W Series

Resistors, So No External Resistors Are

Required

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Latch-Up Performance Exceeds 500 mA Per

JEDEC Standard JESD-17

State-of-the-Art EPIC-IIBE BiCMOS Design

Significantly Reduces Power Dissipation

Typical VOLP (Output Ground Bounce) < 1 V

at VCC = 5 V, TA = 25°C

High-Impedance State During Power Up

and Power Down

Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages, Ceramic Chip Carriers (FK),

Plastic (N) and Ceramic (J) DIPs, and

Ceramic Flat (W) Packages

description

These octal buffers and line drivers are designed

specifically to improve both the performance and

density of 3-state memory address drivers, clock

drivers, and bus-oriented receivers and

transmitters. Together with the SN54ABT2240,

SN74ABT2240A, and ’ABT2241, these devices

provide the choice of selected combinations of

inverting and noninverting outputs, symmetrical

active-low output-enable (OE) inputs, and

complementary OE and OE inputs. These devices

feature high fan-out and improved fan-in.

The outputs, which are designed to sink up to 12 mA, include equivalent 25-W series resistors to reduce

overshoot and undershoot.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;

the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT2244A is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74ABT2244A is characterized for operation from –40°C to 85°C.