Members of the Texas Instruments

WidebusE Family

State-of-the-Art EPIC-IIBE BiCMOS Design

Significantly Reduces Power Dissipation

Distributed VCC and GND Pin Configuration

Minimizes High-Speed Switching Noise

Flow-Through Architecture Optimizes PCB

Layout

High-Impedance State During Power Up

and Power Down

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

Package Options Include Plastic Thin

Shrink Small-Outline (DGG), 300-mil Shrink

Small-Outline (DL) Packages and 380-mil

Fine-Pitch Ceramic Flat (WD) Package

Using 25-mil Center-to-Center Spacings

description

The ’ABT16843 18-bit bus-interface D-type

latches are designed specifically for driving highly

capacitive or relatively low-impedance loads.

They are particularly suitable for implementing

buffer registers, I/O ports, bidirectional bus

drivers, and working registers.

The ’ABT16843 can be used as two 9-bit latches

or one 18-bit latch. The 18 latches are transparent

D-type latches. The device provides true data at

its outputs.

A buffered output-enable (OE) input can be used

to place the nine outputs in either a normal logic

state (high or low logic levels) or a

high-impedance state. The outputs are in the

high-impedance state during power up and power

down. The outputs remain in the high-impedance

state while the device is powered down. In the

high-impedance state, the outputs neither load

nor drive the bus lines significantly. The

high-impedance state and increased drive

provide the capability to drive bus lines without

need for interface or pullup components.