Members of the Texas Instruments

WidebusE Family

State-of-the-Art EPIC-IIBE BiCMOS Design

Significantly Reduces Power Dissipation

Latch-Up Performance Exceeds 500 mA Per

JEDEC Standard JESD-17

Typical VOLP (Output Ground Bounce)

< 1 V at VCC = 5 V, TA = 25°C

Distributed VCC and GND Pin Configuration

Minimizes High-Speed Switching Noise

Flow-Through Architecture Optimizes PCB

Layout

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) Package and

380-mil Fine-Pitch Ceramic Flat (WD)

Package Using 25-mil Center-to-Center

Spacings

description

The ’ABT16652 are 16-bit bus transceivers that

consist of D-type flip-flops and control circuitry

arranged for multiplexed transmission of data

directly from the data bus or from the internal

storage registers. These devices can be used as

two 8-bit transceivers or one 16-bit transceiver.

Output-enable (OEAB and OEBA) inputs are

provided to control the transceiver functions.

Select-control (SAB and SBA) inputs are provided

to select whether real-time or stored data is

transferred. The circuitry used for select control

eliminates the typical decoding glitch that occurs

in a multiplexer during the transition between

stored and real-time data. A low input selects

real-time data, and a high input selects stored

data. Figure 1 illustrates the four fundamental

bus-management functions that can be

performed with the ’ABT16652.

Data on the A- or B-data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions

at the appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control inputs. When SAB

and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops

by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all

other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last

state.