Members of the Texas Instruments

WidebusE Family

State-of-the-Art EPIC-IIBE BiCMOS Design

Significantly Reduces Power Dissipation

Latch-Up Performance Exceeds 500 mA Per

JEDEC Standard JESD-17

Typical VOLP (Output Ground Bounce)

< 1 V at VCC = 5 V, TA = 25°C

Distributed VCC and GND Pin Configuration

Minimizes High-Speed Switching Noise

Flow-Through Architecture Optimizes PCB

Layout

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

Package Options Include Plastic 300-mil

Shrink Small-Outline (DL), Thin Shrink

Small-Outline (DGG), and Thin Very

Small-Outline (DGV) Packages, and 380-mil

Fine-Pitch Ceramic Flat (WD) Package

Using 25-mil Center-to-Center Spacings

description

The SN54ABT16540 and SN74ABT16540A are

inverting 16-bit buffers/drivers composed of two

8-bit sections with separate output-enable gates.

These buffers and bus drivers provide a

high-performance bus interface for wide data

paths.

The 3-state control gate is a 2-input AND gate with

active-low inputs so that if either output-enable

(OE1 or OE2) input is high, all corresponding

outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16540 is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74ABT16540A is characterized for operation from –40°C to 85°C.