Members of the Texas Instruments

Widebus
Family

Output Ports Have Equivalent 25-Ω Series

Resistors, So No External Resistors Are

Required

Typical VOLP (Output Ground Bounce)

<0.8 V at VCC = 5 V, TA = 25°C

High-Impedance State During Power Up

and Power Down

Ioff and Power-Up 3-State Support Hot

Insertion

Distributed VCC and GND Pins Minimize

High-Speed Switching Noise

Flow-Through Architecture Optimizes PCB

Layout

Latch-Up Performance Exceeds 500 mA Per

JEDEC Standard JESD-17

description/ordering information

These 20-bit transparent D-type latches feature

noninverting 3-state outputs designed specifically

for driving highly capacitive or relatively

low-impedance loads. They are particularly

suitable for implementing buffer registers, I/O

ports, bidirectional bus drivers, and working

registers.

The ’ABT162841 devices can be used as two

10-bit latches or one 20-bit latch. While the

latch-enable (1LE or 2LE) input is high, the Q

outputs of the corresponding 10-bit latch follow

the data (D) inputs. When LE is taken low, the

Q outputs are latched at the levels set up at the D

inputs.