1FEATURES

2• A Member of the MuxIt™ Serializer-

Deserializer Building-Block Chip Family

• Supports Deserialization of One Serial Link

Data Channel Input at Rates up to 200 Mbps

• PLL Lock/Valid Input Provided to Enable

Parallel Data and Clock Outputs

• Cascadable With Additional SN65LVDS152

MuxIt Receiver-Deserializers for Wider Parallel

Output Data Channel Widths

• LVDS Compatible Differential Inputs and

Outputs Meet or Exceed the Requirements of

ANSI TIA/EIA-644-A

• LVDS Input and Output ESD Protection

Exceeds 12 kV HBM

• LVTTL Compatible Inputs for Lock/Valid and

Enables Are 5-V Tolerant

• Operates With 3.3-V Supply

• Packaged in 32-Pin DA Thin Shrink

Small-Outline Package With 26-Mil Terminal

Pitch

DESCRIPTION

MuxIt is a family of general-purpose, multiple-chip building blocks for implementing parallel data serializers and

deserializers. The system allows for wide parallel data to be transmitted through a reduced number of

transmission lines over distances greater than can be achieved with a single-ended (e.g., LVTTL or LVCMOS)

data interface. The number of bits multiplexed per transmission line is user selectable, allowing for higher

transmission efficiencies than with other existing fixed ratio solutions. MuxIt utilizes the LVDS (TIA/EIA-644-A)

low voltage differential signaling technology for communications between the data source and data destination.

The MuxIt family initially includes three devices supporting simplex communications: the SN65LVDS150 phase

locked loop frequency multiplier, the SN65LVDS151 serializer-transmitter, and the SN65LVDS152

receiver-deserializer.

The SN65LVDS152 consists of three LVDS differential transmission line receivers, an LVDS differential

transmission line driver, a 10-bit serial-in/parallel-out shift register, plus associated input and output buffers. It

receives serialized data over an LVDS transmission line link, deserializes (demultiplexes) it, and delivers it on

parallel data outputs, DO–0 through DO–9. Data received over the link is clocked at a factor of M times the

original parallel data frequency. The multiplexing ratio M, or number of bits per data clock cycle, is programmed

with configuration pins (M1 → M5) on the companion SN65LVDS150 MuxIt programmable PLL frequency

multiplier. Up to 10 bits of data may be deserialized and output by each SN65LVDS152. Two or more

SN65LVDS152 units may be connected in series (cascaded) to accommodate wider parallel data paths for

higher serialization values. The range of multiplexing ratio M supported by the SN65LVDS150 MuxIt

programmable PLL frequency multiplier is between 4 and 40. Table 1 shows some of the combinations of LCI

and MCI supported by the SN65LVDS150 MuxIt programmable PLL frequency multiplier.