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SN65EPT21DGKR.B中文资料

厂家型号

SN65EPT21DGKR.B

文件大小

543.81Kbytes

页面数量

18

功能描述

3.3-V Differential PECL/LVDS to TTL Translator

数据手册

下载地址一下载地址二到原厂下载

生产厂商

TI2

SN65EPT21DGKR.B数据手册规格书PDF详情

1FEATURES

• 1 ns Propagation Delay

• Fmax > 300MHz

• Operating Range: VCC = 3.0 V to 3.6 V with

GND = 0 V

• 24-mA TTL Output

• Built-In Temperature Compensation

• Drop-In Compatible to the MC10EPT21,

MC100EPT21

APPLICATIONS

• Data and Clock Transmission Over Backplane

• Signaling Level Conversion for Clock or Data

DESCRIPTION

The SN65EPT21 is a differential PECL-to-TTL

translator. It operates on +3.3 V supply and ground

only. The device includes circuitry to maintain inputs

at Vcc/2 when left open.

The VBB pin is a reference voltage output for the

device. When the device is used in single-ended

mode, the unused input should be tied to VBB. This

reference voltage can also be used to bias the input

when it is ac coupled. When it is used, place a

0.01μF decoupling capacitor between VCC and VBB.

Also limit the sink/source current to < 0.5 mA to VBB.

Leave VBB open when it is not used.

The SN65EPT21 is housed in an industry standard

SOIC-8 package and is also available in an optional

TSSOP-8 package.

更新时间:2025-11-4 10:59:00
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