1 Features

1• Qualified for Automotive Applications

• AEC-Q100 Qualified With the Following Results:

– Device Temperature Grade 2: –40°C to

+105°C Ambient Operating Temperature

– Device HBM ESD Classification Level 3A

– Device CDM ESD Classification Level C6

• Implements MIPI® D-PHY Version 1.00.00

Physical Layer Front-End and Display Serial

Interface (DSI) Version 1.02.00

• Single-Channel DSI Receiver Configurable for

One, Two, Three, or Four D-PHY Data Lanes Per

Channel Operating up to 1 Gbps Per Lane

• Supports 18-bpp and 24-bpp DSI Video Packets

with RGB666 and RGB888 Formats

• Maximum Resolution up to 60 fps WUXGA 1920 ×

1200 at 18 bpp and 24 bpp Color With Reduced

Blanking. Suitable for 60 fps 1366 × 768 / 1280 ×

800 at 18 bpp and 24 bpp

• Output for Single-Link LVDS

• Supports Single Channel DSI to Single-Link LVDS

Operating Mode

• LVDS Output Clock Range of 25 MHz to 154 MHz

• LVDS Pixel Clock May be Sourced from Free-

Running Continuous D-PHY Clock or External

Reference Clock (REFCLK)

• 1.8-V Main VCC Power Supply

• Low Power Features Include SHUTDOWN Mode,

Reduced LVDS Output Voltage Swing, Common

Mode, and MIPI Ultra-Low Power State (ULPS)

Support

• LVDS Channel SWAP, LVDS PIN Order Reverse

Feature for Ease of PCB Routing

• Packaged in 64-pin 10-mm × 10-mm HTQFP

(PAP) PowerPAD™ IC Package

2 Applications

• Infotainment Head Unit With Integrated Display

• Infotainment Head Unit With Remote Display

• Infotainment Rear-Seat Entertainment

• Hybrid Automotive Cluster

• Portable Navigation Device

• Navigation

• Industrial Human Machine Interface (HMI) and

Displays

3 Description

The SN65DSI83-Q1 DSI-to-LVDS bridge features a

single-channel MIPI D-PHY receiver front-end

configuration with four lanes per channel operating at

1 Gbps per lane and a maximum input bandwidth of 4

Gbps. The bridge decodes MIPI DSI 18-bpp RGB666

and 24-bpp RGB888 packets and converts the

formatted video data-stream to an LVDS output

operating at pixel clocks operating from 25 MHz to

154 MHz, offering a Single-Link LVDS with four data

lanes per link.

The SN65DSI83-Q1 device can support up to

WUXGA 1920 × 1200 at 60 frames per second, at 24

bpp with reduced blanking. The SN65DSI83-Q1

device is also suitable for applications using 60 fps

1366 × 768/1280 × 800 at 18 bpp and 24 bpp. Partial

line buffering is implemented to accommodate the

data stream mismatch between the DSI and LVDS

interfaces.

The SN65DSI83-Q1 device is implemented in a small

outline 10-mm × 10-mm HTQFP package with a

0.5-mm pitch, and operates across a temperature

range from –40°C to +105°C.