Qualified for Automotive Applications

Wide Operating Voltage Range of 2 V to 6 V

Outputs Can Drive Up To 10 LSTTL Loads

Low Power Consumption, 80-μA Max ICC

Typical tpd = 14 ns

4-mA Output Drive at 5 V

Low Input Current of 1 μA Max

Internal Look-Ahead for Fast Counting

Carry Output for n-Bit Cascading

Synchronous Counting

Synchronously Programmable

description/ordering information

This synchronous, presettable counter features an

internal carry look-ahead for application in

high-speed counting designs. The SN74HC163 is a

4-bit binary counter. Synchronous operation is

provided by having all flip-flops clocked

simultaneously so that the outputs change coincident with each other when instructed by the count-enable

(ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally

associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on

the rising (positive-going) edge of the clock waveform.

This counter is fully programmable; that is, it can be preset to any number between 0 and 9 or 15. As presetting

is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree

with the setup data after the next clock pulse, regardless of the levels of the enable inputs.

The clear function for the SN74HC163 is synchronous. A low level at the clear (CLR) input sets all four of the

flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs.

This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum

count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear

the counter to 0000 (LLLL).

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without

additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function.

Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a

high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse

can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the

level of CLK.