1 Features

• AEC-Q100 qualified for automotive applications:

– Device temperature grade 1: -40°C to +125°C

– Device HBM ESD classification level 2

– Device CDM ESD classification level C4B

• Available in wettable flank QFN package

• Operating range 2V to 5.5V VCC

• Low delay, 18.8ns at 5V, 15pF load

• Supports 130MHz at 5V, 15pF load

• Latch-up performance exceeds 250mA

per JESD 17

2 Applications

• Synchronize data to clock

• Simple memory – 8 bits

3 Description

The SN74AHC273-Q1 contains eight positive-edgetriggered

D-type flip-flops with a direct active low clear

( CLR) input.

Information at the data (D) inputs meeting the setup

time requirements is transferred to the Q outputs on

the positive-going edge of the clock (CLK) pulse.

Clock triggering occurs at a particular voltage level

and is not related directly to the transition time of the

positive-going pulse. When CLK is at either the high

or low level, the D input has no effect at the output.