Members of the Texas Instruments

WidebusE Family

EPICE (Enhanced-Performance Implanted

CMOS) Process

Operating Range 2-V to 5.5-V VCC

Distributed VCC and GND Pins Minimize

High-Speed Switching Noise

Flow-Through Architecture Optimizes PCB

Layout

Latch-Up Performance Exceeds 250 mA Per

JESD 17

Package Options Include Plastic Shrink

Small-Outline (DL), Thin Shrink

Small-Outline (DGG), and Thin Very

Small-Outline (DGV) Packages and 380-mil

Fine-Pitch Ceramic Flat (WD) Package

Using 25-mil Center-to-Center Spacings

description

The ’AHC16541 devices are noninverting 16-bit

buffers composed of two 8-bit sections with

separate output-enable signals. For either 8-bit

buffer section, the two output-enable (1OE1 and

1OE2 or 2OE1 and 2OE2) inputs must be low for

the corresponding Y outputs to be active. If either

output-enable input is high, the outputs of that

8-bit buffer section are in the high-impedance

state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54AHC16541 is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74AHC16541 is characterized for operation from –40°C to 85°C.