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SN54ABTH16244中文资料

厂家型号

SN54ABTH16244

文件大小

477.54Kbytes

页面数量

17

功能描述

16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

数据手册

下载地址一下载地址二到原厂下载

生产厂商

TI2

SN54ABTH16244数据手册规格书PDF详情

Members of the Texas Instruments

WidebusE Family

State-of-the-Art EPIC-IIBE BiCMOS Design

Significantly Reduces Power Dissipation

Latch-Up Performance Exceeds 500 mA Per

JESD 17

Typical VOLP (Output Ground Bounce)

<1 V at VCC = 5 V, TA = 25°C

Distributed VCC and GND Pins Minimize

High-Speed Switching Noise

Flow-Through Architecture Optimizes PCB

Layout

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Package Options Include Plastic Shrink

Small-Outline (DL), Thin Shrink

Small-Outline (DGG), Thin Very

Small-Outline (DGV) Packages, and 380-mil

Fine-Pitch Ceramic Flat (WD) Packages

description

The ’ABTH16244 devices are 16-bit buffers and

line drivers designed specifically to improve both

the performance and density of 3-state memory

address drivers, clock drivers, and bus-oriented

receivers and transmitters. These devices can be

used as four 4-bit buffers, two 8-bit buffers, or one

16-bit buffer. These devices provide true outputs

and symmetrical active-low output-enable (OE)

inputs.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN54ABTH16244 is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74ABTH16244 is characterized for operation from –40°C to 85°C.

SN54ABTH16244产品属性

  • 类型

    描述

  • 型号

    SN54ABTH16244

  • 制造商

    TI

  • 制造商全称

    Texas Instruments

  • 功能描述

    16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

更新时间:2025-11-27 16:50:00
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