State-of-the-Art EPIC-IIBE BiCMOS Design

Significantly Reduces Power Dissipation

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Latch-Up Performance Exceeds 500 mA Per

JEDEC Standard JESD-17

Typical VOLP (Output Ground Bounce) < 1 V

at VCC = 5 V, TA = 25°C

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages, Ceramic Chip Carriers (FK),

Plastic (N) and Ceramic (J) DIPs, and

Ceramic Flat (W) Package

description

The ’ABT540 octal buffers and line drivers are

ideal for driving bus lines or buffer memory

address registers. The devices feature inputs and

outputs on opposite sides of the package that

facilitate printed circuit board layout.

The 3-state control gate is a 2-input AND gate with

active-low inputs so that if either output-enable

(OE1 or OE2) input is high, all corresponding

outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT540 is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74ABT540 is characterized for operation from –40°C to 85°C.