Members of the Texas Instruments

WidebusE Family

State-of-the-Art EPIC-IIBE BiCMOS Design

Significantly Reduces Power Dissipation

Latch-Up Performance Exceeds 500 mA Per

JEDEC Standard JESD-17

Typical VOLP (Output Ground Bounce) < 1 V

at VCC = 5 V, TA = 25°C

Distributed VCC and GND Pin Configuration

Minimizes High-Speed Switching Noise

Flow-Through Architecture Optimizes PCB

Layout

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages and 380-mil

Fine-Pitch Ceramic Flat (WD) Package

Using 25-mil Center-to-Center Spacings

description

The ’ABT16952 are 16-bit registered transceivers

that contain two sets of D-type flip-flops for

temporary storage of data flowing in either

direction. The ’ABT16952 can be used as two 8-bit

transceivers or one 16-bit transceiver. Data on the

A or B bus is stored in the registers on the

low-to-high transition of the clock (CLKAB or

CLKBA) input provided that the clock-enable

(CLKENAB or CLKENBA) input is low. Taking the

output-enable (OEAB or OEBA) input low

accesses the data on either port.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16952 is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74ABT16952 is characterized for operation from –40°C to 85°C.