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description

These J-K flip-flops are based on the master-slave

principle and each has AND gate inputs for entry into the

master section which are controlled by the clock pulse.

The clock pulse also regulates the state of the coupling

transistors which connect the master and slave sections.

The sequence of operation is as follows:

1. Isolate slave from master

2. Enter information from AND gate inputs to

master

3. Disable AND gate inputs

4. Transfer information from master to slave

The logical states of the J and K inputs must not be

allowed to change when the clock pulse is in a high

state.

The SN5472, and the SN54H72 are characterized for

operation over the full military temperature range of

~55°C to 126°C. The SN7472 is characterized for

operation from 0°C to 70°C.