1FEATURES

2• True IEEE 1149.1 Hierarchical and Multidrop

Addressable Capability

• The 8 Address Inputs Support up to 249

Unique Slot Addresses, an Interrogation

Address, Broadcast Address, and 4 Multi-Cast

Group Addresses (Address 000000 is

Reserved)

• 7 IEEE 1149.1-Compatible Configurable Local

Scan Ports

• Bi-directional Backplane and LSP0 Ports are

Interchangeable Slave Ports

• Capable of Ignoring TRST of the Backplane

Port when it Becomes the Slave.

• Stitcher Mode Bypasses Level 1 and 2

Protocols

• Mode Register0 Allows Local TAPs to be

Bypassed, Selected for Insertion into the Scan

Chain Individually, or Serially in Groups of

Two or Three

• Transparent Mode can be Enabled with a

Single Instruction to Conveniently Buffer the

Backplane IEEE 1149.1 Pins to Those on a

Single Local Scan Port

• General Purpose Local Port Pass Through Bits

are Useful for Delivering Write Pulses for Flash

Programming or Monitoring Device Status.

• Known Power-Up State

• TRST on all Local Scan Ports

• 32-bit TCK Counter

• 16-bit LFSR Signature Compactor

• Local TAPs can Become TRI-STATE via the OE

Input to Allow an Alternate Test Master to Take

Control of the Local TAPs (LSP0-3 have a TRISTATE

Notification Output)

• 3.0-3.6V VCC Supply Operation

• Supports Live Insertion/Withdrawal

DESCRIPTION

The SCANSTA112 extends the IEEE Std. 1149.1 test

bus into a multidrop test bus environment. The

advantage of a multidrop approach over a single

serial scan chain is improved test throughput and the

ability to remove a board from the system and retain

test access to the remaining modules. Each

SCANSTA112 supports up to 7 local IEEE1149.1

scan chains which can be accessed individually or

combined serially.

Addressing is accomplished by loading the instruction

register with a value matching that of the Slot inputs.

Backplane and inter-board testing can easily be

accomplished by parking the local TAP Controllers in

one of the stable TAP Controller states via a Park

instruction. The 32-bit TCK counter enables built in

self test operations to be performed on one port while

other scan chains are simultaneously tested.

The STA112 has a unique feature in that the

backplane port and the LSP0 port are bidirectional.

They can be configured to alternatively act as the

master or slave port so an alternate test master can

take control of the entire scan chain network from the

LSP0 port while the backplane port becomes a slave.