1 Features

• AEC-Q100 qualified with the following results:

– Device temperature grade 1: –40°C to +125°C

ambient operating temperature TA

• ASIL D Functional Safety-Compliant (Targeted for

TPS37102-Q1)

– Documentation to aid ISO 26262 system design

– Systematic capability up to ASIL D targeted

– Hardware capability up to ASIL D targeted

• Functional Safety-Capable (TPS37100-Q1)

– Documentation available to aid functional safety

system design

• Wide supply voltage range: 3V to 105V

• Low quiescent current: 5μA

• High threshold accuracy: 1.1% (maximum)

• -95V reverse polarity protection on SENSE

• 5μs fast UV/OV monitor for 24V/48V systems

• Integrated buffer (AOUT) for supply voltage

measurement with enable pin

• Fixed and programmable release time delay

• Fixed and programmable sense time delay

• Open-drain, active-low output: OUT A and OUT B

• BIST and Latch available for TPS37102-Q1

2 Applications

• Battery management unit

• DC/DC converter system

• 2-wheeler and 3-wheeler traction drive

• Low-voltage battery system

• Traction inverter

3 Description

The TPS37100-Q1 and TPS37102-Q1 are 105V input

voltage supervisors with low quiescent current (5uA),

fast detection time, and an integrated buffer for supply

voltage measurements. This family of devices can be

connected directly to a 24V / 48V / 72V battery or

voltage rail for continuous monitoring of over (OV)

or under (UV) voltage conditions. Wide hysteresis

voltage options are available to ignore false output

deassertions that are be caused by battery voltage

transients.

The TPS37100-Q1 and TPS37102-Q1 include two

outputs (OUT A and OUT B) that are used as

separate OV and UV fault monitors enabling system

to take different action based on the fault that occurs.

Additionally, the AOUT pin provides a scaled down

SENSE pin voltage output and is intended to be

sampled by ADC for supply voltage measurements.

The user can choose the scaling factor desired based

on the orderable part selected. The TPS37102-Q1

comes with BIST which is implemented at start-up to

verify device health as well as an optional latching

feature on OUT A to help the system bring into a safe

state when critical faults occurs.