1.1 Features

12

• Integrated VCO with Very Low Phase Noise

Floor

• Integrated Integer-N PLL with Outstanding

Normalized Phase Noise Contribution of -224

dBc/Hz

• VCO Divider Values of 2 to 8 (All Divides)

– Bypassable with VCO Mux When Not in 0-

delay Mode

• Channel Divider Values of 1, 2 to 510 (Even

Divides)

• LVDS and LVPECL Clock Outputs

• Partially Integrated Loop Filter

1.2 Target Applications

• Data Converter Clocking

• Networking, SONET/SDH, DSLAM

• Wireless Infrastructure

• Medical

• Test and Measurement

• Military / Aerospace

• Dedicated Divider and Delay Blocks on Each

Clock Output

• 0-delay Outputs

• Internal or External Feedback of Output Clock

• Delay Blocks on N and R Phase Detector Inputs

for Lead/Lag Global Skew Adjust

• Pin Compatible Family of Clocking Devices

• 3.15 to 3.45 V Operation

• Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)

• 200 fs RMS Clock Generator Performance (10

Hz to 20 MHz) with a clean input clock