1FEATURES

2• SDTV/HDTV Serial Digital Video Standard

Compliant

• Supports 270 Mbps, 360 Mbps, 540 Mbps,

1.483 Gbps and 1.485 Gbps Serial Video Data

Rates with Auto-Detection

• LSB De-Dithering Option

• Uses Low-Cost 27MHz Crystal or Clock

Oscillator Reference

• Fast VCO Lock Time: < 500 μs at 1.485 Gbps

• Built-in Self-Test (BIST) and Video Test Pattern

Generator (TPG)

(1) Patent Applications Made or Pending

• Automatic EDH/CRC Word and Flag

Processing

• Ancillary Data FIFO with Extensive Packet

Handling Options

• Adjustable, 4-Deep Parallel Output Video Data

FIFO

• Flexible Control and Configuration I/O Port

• LVCMOS Compatible Control Inputs and Clock

and Data Outputs

• LVDS and ECL-Compatible, Differential, Serial

Inputs

• 3.3V I/O Power Supply and 2.5V Logic Power

Supply Operation

• Low Power: Typically 850mW

• 64-Pin TQFP Package

• Commercial Temperature Range 0°C to +70°C

APPLICATIONS

• SDTV/HDTV Serial-to-Parallel Digital Video

Interfaces for:

– Video Editing Equipment

– VTRs

– Standards Converters

– Digital Video Routers and Switchers

– Digital Video Processing and Editing

Equipment

– Video Test Pattern Generators and Digital

Video Test Equipment

– Video Signal Generators

DESCRIPTION

The LMH0031 SMPTE 292M / 259M Digital Video

Deserializer/Descrambler with Video and Ancillary

Data FIFOs is a monolithic integrated circuit that

deserializes and decodes SMPTE 292M, 1.485Gbps

(or 1.483Gbps) serial component video data, to 20-bit

parallel data with a synchronized parallel word-rate

clock. It also deserializes and decodes SMPTE 259M,

270Mbps, 360Mbps and SMPTE 344M (proposed)

540Mbps serial component video data, to 10-bit

parallel data. Functions performed by the LMH0031

include: clock/data recovery from the serial data,

serial-to-parallel data conversion, SMPTE standard

data decoding, NRZI-to-NRZ conversion, parallel data

clock generation, word framing, CRC and EDH data

checking and handling, Ancillary Data extraction and

automatic video format determination. The parallel

video output features a variable-depth FIFO which

can be adjusted to delay the output data up to 4

parallel data clock periods. Ancillary Data may be

selectively extracted from the parallel data through

the use of masking and control bits in the

configuration and control registers and stored in the

on-chip FIFO. Reverse LSB dithering is also

implemented.