1 Features

• 650V 70mΩ GaN power FET with integrated gate

driver

– >200V/ns FET hold-off

– Adjustable slew rates for optimization of

switching performance and EMI mitigation

• 10V/ns to 100V/ns turn-on slew rates

• 10V/ns to full speed turn-off slew rates

– Operates with supply pin and input logic pin

voltage range from 9V to 26V

• Robust protection

– Cycle-by-cycle overcurrent and latched shortcircuit

protection with <300ns response

– Withstands 720V surge

– Self-protection from internal overtemperature

and UVLO monitoring

• Advanced power management

– LMG3656R070 includes zero-voltage detection

(ZVD) feature that facilitates soft-switching

converters

– LMG3657R070 includes zero-current detection

(ZCD) feature that facilitates soft-switching

converters

• 9.8mm × 11.6mm TOLL package with thermal pad

2 Applications

• Open rack server PSU

• Merchant telecom rectifiers

• Common redundant power supply

• Uninterruptible power supplies

• Solar inverters and industrial motor drives

3 Description

The LMG365xR070 GaN FET with integrated driver

and protection is targeted at switch-mode power

converters and enables designers to achieve new

levels of power density and efficiency.

Adjustable gate driver strength allows the control

of turn-on and maximum turn-off slew rates

independently, which can be used to actively control

EMI and optimize switching performance. Turn on

slew rate varies from 10V/ns to 100V/ns, while

the turn off slew rate can be limited from 10V/ns

to a maximum based on the magnitude of load

current. Protection features include under-voltage

lockout (UVLO), cycle-by-cycle overcurrent limit,

and short-circuit and overtemperature protection.

The LMG3651R070 provides a 5V LDO output on

LDO5V pin that powers external digital isolators. The

LMG3656R070 includes the zero-voltage detection

(ZVD) feature which provides a pulse output from the

ZVD pin when zero-voltage switching is realized. The

LMG3657R070 includes the zero-current detection

(ZCD) feature that sets the ZCD pin high when the

drain-to-source current is negative and transitions to

low upon detecting the zero-crossing point.