1FEATURES

2• 24-bit RGB Interface Support up to 640 x 480

VGA Format

• Optional 24 to 18-bit Dithering

• Optional Look Up Table for Independent Color

Correction

• MPL-1 Physical Layer

• SPI Interface for Look Up Table Control and

Loading

• Low Power Consumption & Powerdown State

• Level Translation Between Host and Display

• Optional Auto Power Down on STOP PCLK

• Frame Sequence Bits Auto Resync upon Data

or Clock Error

• 1.6V to 2.0V Core / Analog Supply Voltage

• 1.6V to 3.0V I/O Supply Voltage Range

SYSTEM BENEFITS

• Dithered Data Reduction

• Independent RGB Color Correction

• 24-bit Color Input

• Small Interface, Low Power and Low EMI

• Intrinsic Level Translation

DESCRIPTION

The LM2512A is a MPL Serializer (SER) that

performs a 24-bit to 18-bit Dither operation and

serialization of the video signals to Mobile Pixel link

(MPL) levels on only 3 or 4 active signals. An optional

Look Up Table (Three X 256 X 8 bit RAM) is also

provided for independent color correction. 18-bit

Bufferless or partial buffer displays from QVGA (320

x 240) up to VGA (640 x 480) pixels can utilize a 24-

bit video source.

The interconnect is reduced from 28 signals to only 3 or 4 active signals with the LM2512A and companion

deserializer easing flex interconnect design, size

constraints and cost.

The LM2512A SER resides by the application,

graphics or baseband processor and translates the

wide parallel video bus from LVCMOS levels to serial

Mobile Pixel Link levels for transmission over a flex

cable (or coax) and PCB traces to the DES located

near or in the display module.

When in Power_Down, the SER is put to sleep and

draws less than 10μA. The link can also be powered

down by stopping the PCLK (DES dependant) or by

the PD* input pins.

The LM2512A provides enhanced AC performance

over the LM2512. It implements the physical layer of

the MPL-1 and uses a single-ended current-mode

transmission.