1 Features

• AEC-Q100 qualified with the following results:

– Device temperature Grade 1: –40°C to +125°C

ambient operating temperature range

• Up to 50Mbps data rate

• Robust SiO2 isolation barrier

• Functional Isolation (DBQ-16):

– 400VRMS , 566VDC working voltage

– 707VRMS , 1000VDC transient voltage (60s)

• Wide temperature range: –40°C to 125°C

• ±150kV/μs typical CMTI

• Supply range: 1.71V to 5.5V

• Default output high ( ISO654x-Q1 ) and low

( ISO654xF-Q1 ) options

• 1.5mA per channel typical at 1Mbps and 3.3V

(ISO6540-Q1)

• Low propagation delay: 11ns typical at 3.3V

• Robust electromagnetic compatibility (EMC)

– System-level ESD, EFT, and surge immunity

– Low emissions

• SSOP (DBQ-16) Package

2 Applications

• Hybrid, electric and power train system (EV/HEV)

– Battery management system (BMS)

– On-board charger

– DC/DC converter

– Inverter and motor control

3 Description

The ISO654x-Q1 devices are general purpose

functional isolators for cost sensitive, space

constrained applications that require isolation for nonsafety

applications. The isolation barrier supports a

working voltage of 400VRMS / 566VDC and transient

over voltages of 707VRMS / 1000VDC .

The ISO654x-Q1 devices provide high EMC

performance while isolating CMOS or LVCMOS digital

I/Os. ISO654x-Q1 uses SiO2 as the isolation barrier.

Each isolation channel has a logic input and output

buffer separated by the insulation barrier. These

devices come with enable pins that can be used to

put the respective outputs in high impedance.

The ISO6540-Q1 and ISO6540F-Q1 devices have all

channels in the forward direction. The ISO6541-Q1

and ISO6541F-Q1 devices have one reverse-direction

channel. The ISO6542-Q1 and ISO6542F-Q1 devices

have two reverse-direction channels.

In the event of input power or signal loss, the default

output is high for devices without the suffix F and

low for devices with the suffix F. See Section 7.4 for

further details.

These devices help prevent noise currents on GPIOs

or data buses such as SPI, UART and CAN

from causing data corruption or damaging sensitive

circuitry. Through chip design and layout techniques,

the electromagnetic compatibility of the devices have

been significantly enhanced to ease system-level

design.