1 Features

Real-time Processing

• Three C29x 64-bit CPUs (CPU1, CPU2, CPU3)

running at 200MHz

– 2x signal chain performance versus C28x with

improved pipeline

– Split lock and lockstep operating modes

• C29x CPU architecture

– Byte addressability

– High-performance real-time control with low

latency

– High-performance DSP and general-purpose

processing capabilities

– VLIW CPU executes 1 to 8 instructions in

parallel

– Fully protected pipeline

– 8/16/32/64-bit single-cycle memory operations,

up to two 64-bit memory reads and one 64-bit

memory write in a single-cycle

– IEEE 32-bit and 64-bit floating operations

– 32-bit and 64-bit trigonometric operations

– HW interrupt prioritization and nesting

– 11-cycle real-time interrupt response

– Atomic operations with memory protection

– Multi safe island code execution managed in

hardware

Memory

• 4MB of CPU-mappable flash (ECC-protected)

capable of supporting Firmware Over the Air

(FOTA) with A/B swap and LFU

• 256KB of Data-only Flash (ECC-protected)

• 452KB of RAM (ECC-protected)

• Dedicated 512KB Flash and 40KB RAM memories

for HSM (ECC-protected)

• Built in ECC logic for system-wide safety

Safety Peripherals

• CPU1 and CPU2 lockstep

– CPU1 and CPU2 splitlock mode is also

available (for applications not needing

functional safety or using methods like

Reciprocal Comparison with multiple CPUs)

• Logic Power-On Self-Test (LPOST)

• Memory Power-On Self-Test (MPOST)

• Error Signaling Module (ESM)

• Dual-clock Comparator (DCC)

• Waveform Analyzer and Diagnostics (WADI)

• Context-sensitive Memory and Peripheral

Protection with SSU

• Safety Interconnect (SIC)

• Functional Safety-Compliant targeted

– Developed for functional safety applications

– Documentation to aid ISO 26262 and IEC

61508 system design will be available upon

production release

– Systematic capability up to ASIL D and SIL 3

targeted

– Hardware capability up to ASIL D and SIL 3

targeted

• Safety-related certification

– ISO 26262 certification up to ASIL D and IEC

61508 SIL 3 by TÜV SÜD planned

Security

• Hardware Security Module (HSM)

– Independently running Arm® Cortex®-M4 based

security controller subsystem at 100MHz

– 512KB of flash (ECC-protected)

– 36KB of RAM (ECC-protected)

– Secure key storage

– Secure BOOT

– Secure Debug

– Dedicated 8-channel Real-Time Direct Memory

Access (RTDMA) controller

– EVITA-full support

– FOTA with A/B swap

– Hardware cryptographic accelerators

• Asymmetric cryptography - RSA, ECC, SM2

• Symmetric cryptography - AES, SM4

• Hash operations - SHA2, HMAC, SM3

• True Random Number Generator

• Safety and Security Unit (SSU)

– Advanced Real-Time Safety and Security

• 64 Memory Access Protection Ranges per

CPU

• Up to 15 user LINKs and 7 stack pointers

per CPU for hardware code isolation

• Power-on Self-test (POST) capability

• FOTA and LFU support with rollback control

Analog Subsystem

• Five Analog-to-Digital Converters (ADCs)

– Two 16-bit ADCs, 1.19MSPS each

– Three 12-bit ADCs, 3.92MSPS each

– Up to 80 single-ended or 16 differential inputs

– 40 redundant input channels for flexibility

– Separate sample-and-hold (S/H) on each ADC

for simultaneous sampling

– Hardware post-processing of conversions

– Hardware oversampling (up to 128x) and

undersampling modes, with accumulation,

averaging and outlier rejection

– Programmable delay from SOC trigger to start

of conversion

– Ten ADC Safety Checkers for comparison

of conversion results across multiple ADC

modules

• 12 windowed comparators with 12-bit Digital-to-

Analog Converter (DAC) references

– Connection options for internal temperature

sensor and ADC reference

• Two 12-bit buffered DAC outputs

Control Peripherals

• 36 Pulse Width Modulator (PWM) channels, all

with high-resolution capability (HRPWM)

– Minimum Dead-Band Logic (MINDB)

– Illegal Combo Logic (ICL) for standard and high

resolution

– Diode Emulation (DE) support

– Multilevel shadowing on XCMP

• Six Enhanced Capture (eCAP) modules

– High-resolution Capture (HRCAP) available on

two of the six eCAP modules

– Two new monitor units for edge, pulse width

and period that can be coupled with ePWM

strobes and trip events

– Increased 256 multiplexed capture inputs

– New ADC SOC generation capability

• Six Enhanced Quadrature Encoder Pulse (eQEP)

modules

• 16 Sigma-Delta Filter Module (SDFM) input

channels, 2 independent filters per channel

• Embedded Pattern Generator (EPG)

• Configurable Logic Block (CLB)

– Six tiles

– Augments existing peripheral capability

– Supports position manager solutions

Communications Peripherals

• EtherCAT® SubordinateDevice (or SubDevice)

Controller (ESC)

• Fast Serial Interface (FSI) with four transmitters

and four receivers

• Five high-speed (up to 50MHz) SPI ports (pinbootable)

• Six High-Speed Universal Asynchronous Receiver/

Transmitters (UARTs) (pin-bootable)

• Two I2C interfaces (pin-bootable)

• Two Local Interconnect Network (LIN) (supports

SCI)

• Power-Management Bus (PMBus) interface

(supports I2C)

• Six Single Edge Nibble Transmission interface

(SENT)

• Six Controller Area Networks with Flexible Data

Rate (CAN FD/MCAN) (pin-bootable)

Systems Peripherals

• External Memory Interface (EMIF) with ASRAM

and SDRAM support

• Two 10-channel Real-Time Direct Memory Access

(RTDMA) controllers with MPU

• Up to 190 usable signal pins

– 136 General-Purpose Input/Output (GPIO) pins

– 80 analog pins (26 AGPIOs included in GPIOs)

– 5V fail-safe and tolerant capability on 6 GPIOs

for PMBUS/I2C/SENT support

• Peripheral Interrupt Priority and Expansion (PIPE)

• Low-power mode (LPM) support

• Embedded Real-time Analysis and Diagnostic

(ERAD)

Clock and System Control

• On-chip crystal oscillator

• Windowed watchdog timer module

• Missing clock detection circuitry

• 1.25V core, 3.3V I/O design

– Internal VREG for 1.25V generation

– Brownout reset (BOR) circuit

Package Options:

• Lead-free, green packaging

• 256-ball New Fine Pitch Ball Grid Array (nFBGA)

[ZEX suffix], 13mm x 13mm/0.8mm pitch

• 176-pin Thermally Enhanced Thin Quad Flatpack

(HTQFP) [PTS suffix], 22mm x 22mm/0.4mm pitch

• 144-pin HTQFP [RFS suffix],

18mm x 18mm/0.4mm pitch

• 100-pin HTQFP [PZS suffix],

14mm x 14mm/0.4mm pitch

Recommended TPS653860-Q1 and TPS650366-Q1

Power Management ICs (PMIC)

• Companion PMICs specially designed to meet

device power supply requirements

• Flexible mapping and factory programmed

configurations to support different use cases

• Functional safety compliant PMICs to support

external voltage monitoring and watchdog timer

MCU safety requirements

Temperature

• Ambient (TA): –40°C to 125°C

2 Applications

• On-board charger (OBC) with or without Host

Integration

• HEV/EV DC/DC converter

• HEV/EV powertrain integration

• Electric power steering (EPS)

• Traction Inverter

• HVAC large commercial motor control

• Automated sorting equipment

• CNC control

• Central inverter

• String inverter

• Inverter & motor control

• Linear motor segment controller

• Servo drive control module

• Industrial AC-DC

• Three phase UPS

• Merchant network and server PSU

3 Description

The F29H85x, F29P58x, and F29P32x are members of the C2000™ real-time microcontroller family of scalable,

ultra-low latency MCUs designed for efficiency in power electronics, motor control, and beyond, including but not

limited to: high power density, high switching frequencies, and supporting the use of GaN and SiC technologies.

The F29 product families feature the next-generation C29 CPU core, leading the industry with 2x performance

from the previous-generation C28 CPU core. The C29 core also supports byte-addressing, with data types fully

compatible with other popular CPU architectures, including the Arm® architecture, enabling a smooth migration

for customers looking to go to market quickly. For more information, see The C29 CPU – Unrivaled Real-Time

Performance with Optimized Architecture on C2000™ MCUs technical white paper.

These include such applications as:

• HEV/EV powertrain – helping enable single-stage OBC architectures

– On-board chargers

– DC/DC converters

– Integrated powertrain

• Safety and chassis applications:

– Electric power steering

– Braking

• Motor control

– Traction inverter motor control – enabling advanced and sophisticated control techniques to improve

traction system efficiency

– HVAC motor control

– Mobile robot motor control

• Solar inverters

– Central inverter

– Micro inverter

– String inverter

• Digital power

• Industrial motor drives

• EV charging infrastructure

The real-time control subsystem has up to three 200MHz C29x CPU cores (400MIPS per core, up to 1200MIPS

on F29H85x). Due to the C29 CPU architecture and tightly coupled peripherals (PWM, ADC, CMPSS), we see

better performance with a 200MHz C29 core versus our competition running at higher CPU clock speed for

certain applications – backed by customer benchmarks.

Many features are included to support a system-level ASIL D functional safety solution. The C29x CPU1

and CPU2 cores can be put in lockstep for detection of permanent and transient faults. Logic Power-On

Self-Test (LPOST) and Memory Power-On Self-Test (MPOST) provide start-up detection of latent faults. Safe

interconnects provide fault detection between the CPU and the peripherals. The ADC safety checker compares

ADC conversion results from multiple ADC modules without additional CPU cycles. The Waveform Analyzer and

Diagnostic (WADI) can monitor multiple signals for proper operation and take action to make sure a safe state is

maintained. The device architecture features a Safe Interconnect (SIC) for end-to-end code and data safety, with

CPU-based ECC protection for all memories and peripheral endpoints.