1FEATURES

2• 25–80 MHz 16:1/1:16 Serializer/Deserializer

(2.56Gbps Full Duplex Throughput)

• Independent Transmitter and Receiver

Operation With Separate Clock, Enable, Power

Down Pins

• Hot Plug Protection (Power Up High

Impedance) and Synchronization (Receiver

Locks To Random Data)

• Wide +/−5% Reference Clock Frequency

Tolerance for Easy System Design Using

Locally-Generated Clocks

• Line and Local Loopback Modes

• Robust BLVDS Serial Transmission Across

Backplanes and Cables for Low EMI

• No External Coding Required

• Internal PLL, No External PLL Components

Required

• Single +3.3V Power Supply

• Low Power: 104mA (typ) Transmitter, 119mA

(typ) Receiver at 80MHz

• ±100mV Receiver Input Threshold

• Loss of Lock Detection and Reporting Pin

• Industrial −40 to +85°C Temperature Range

• >2.5kV HBM ESD

• Compact, Standard 80-Pin LQFP Package

DESCRIPTION

The DS92LV16 Serializer/Deserializer (SERDES) pair

transparently translates a 16–bit parallel bus into a

BLVDS serial stream with embedded clock

information. This single serial stream simplifies

transferring a 16-bit, or less bus over PCB traces and

cables by eliminating the skew problems between

parallel data and clock paths. It saves system cost by

narrowing data paths that in turn reduce PCB layers,

cable width, and connector size and pins.

This SERDES pair includes built-in system and

device test capability. The line loopback and local

loopback features provide the following functionality:

the local loopback enables the user to check the

integrity of the transceiver from the local parallel-bus

side and the system can check the integrity of the

data transmission line by enabling the line loopback.

The DS92LV16 incorporates BLVDS signaling on the

high-speed I/O. BLVDS provides a low power and low

noise environment for reliably transferring data over a

serial transmission path. The equal and opposite

currents through the differential data path control EMI

by coupling the resulting fringing fields together.