1 Features

1• Bus LVDS Signaling

• Propagation Delay: Driver 2.3 ns Max, Receiver

3.2 ns Max

• Low power CMOS Design

• 100% Transition Time 1 ns Driver Typical, 1.3 ns

Receiver Typical

• High Signaling Rate Capability (above 155 Mbps)

• 0.1 V to 2.3 V Common Mode Range for

VID = 200 mV

• 70 mV Receiver Sensitivity

• Supports Open and Terminated Failsafe on Port

Pins

• 3.3-V Operation

• Glitch Free Power up/down (Driver & Receiver

Disabled)

• Light Bus Loading (5 pF Typical) per Bus LVDS

Load

• Balanced Output Impedance

• Product Offered in 44 Pin WQFN Package

• High Impedance Bus Pins on Power Off

(VCC = 0 V)

2 Applications

Designed for Double Termination Applications

3 Description

The DS92LV040A is one in a series of Bus LVDS

transceivers designed specifically for high speed, low

power backplane or cable interfaces. The device

operates from a single 3.3-V power supply and

includes four differential line drivers and four

receivers. To minimize bus loading, the driver outputs

and receiver inputs are internally connected. The

device also features a flow through pin out which

allows easy PCB routing for short stubs between its

pins and the connector.

The driver translates 3-V LVTTL levels (single-ended)

to differential Bus LVDS (BLVDS) output levels. This

allows for high speed operation while consuming

minimal power and reducing EMI. In addition, the

differential signaling provides common mode noise

rejection greater than ±1 V.

The receiver threshold is less than +0/−70 mV. The

receiver translates the differential Bus LVDS to

standard (LVTTL/LVCMOS) levels. (See the

Application Information Section for more details.)