1 Features

1• Integrated HDCP Cipher Engine with On-Chip Key

Storage

• Bidirectional Control Channel Interface with I2C

Compatible Serial Control Bus

• Low EMI FPD-Link Video Input

• Supports High Definition (720p) Digital Video

Format

• 5-MHz to 85-MHz PCLK Supported

• RGB888 + VS, HS, DE and I2S Audio Supported

• Up to 4 I2S Digital Audio Inputs for Surround

Sound Applications

• 4 Bidirectional GPIO Channels with 2 Dedicated

Pins

• Single 3.3-V Supply with 1.8-V or 3.3-V

Compatible LVCMOS I/O Interface

• AC-Coupled STP Interconnect up to 10 Meters

• DC-Balanced & Scrambled Data with Embedded

Clock

• Supports HDCP Repeater Application

• Internal Pattern Generation

• Low Power Modes Minimize Power Dissipation

• Automotive Grade Product: AEC-Q100 Grade 2

Qualified

• > 8-kV HBM and ISO 10605 ESD Rating

• Backward Compatible Modes

2 Applications

• Automotive Displays for Navigation

• Rear Seat Entertainment Systems

3 Description

The DS90UH927Q-Q1 serializer, in conjunction with

a DS90UH928Q-Q1 or DS90UH926Q-Q1

deserializer, provides a solution for secure distribution

of content-protected digital video within automotive

entertainment systems. This chipset translates a

FPD-Link video interface into a single-pair high-speed

serialized interface. The digital video data is protected

using the industry standard High-Bandwidth Digital Content Protection (HDCP) copy protection scheme.

The FPD-Link III serial bus scheme supports full

duplex, high speed forward channel data

transmission and low-speed back channel

communication over a single differential link.

Consolidation of audio, video, and control data over a

single differential pair reduces the interconnect size

and weight, while also eliminating skew issues and

simplifying system design.

The DS90UH927Q-Q1 serializer embeds the clock,

content protects the data payload, and level shifts the

signals to high-speed differential signaling. Up to 24

RGB data bits are serialized along with three video

control signals, and up to four I2S data inputs.

The FPD-Link data interface allows for easy

interfacing with data sources while also minimizing

EMI and bus width. EMI on the high-speed FPD-Link

III bus is minimized using low voltage differential

signaling, data scrambling and randomization, and

dc-balancing.

The HDCP cipher engine is implemented in both the

serializer and deserializer. HDCP keys are stored in

on-chip memory.