1 Features

1• AEC-Q100 Qualified for Automotive Applications

– Device Temperature Grade 2: –40°C to

+105°C Ambient Operating Temperature

– Device HBM ESD Classification Level 3B

– Device CDM ESD Classification Level C6

– Device MM ESD Classification Level M3

• Integrated HDCP Cipher Engine With On-Chip

Key Storage

• Bidirectional Control Interface Channel Interface

With I2C Compatible Serial Control Bus

• Supports High-Definition (720p) Digital Video

Format

• RGB888 + VS, HS, DE and I2S Audio Supported

• 5- to 85-MHz PCLK Supported

• Single 3.3-V Operation With 1.8-V or 3.3-V

Compatible LVCMOS I/O Interface

• AC-Coupled STP Interconnect up to 10 Meters

• Parallel LVCMOS Video Outputs

• DC-Balanced and Scrambled Data With

Embedded Clock

• Adaptive Cable Equalization

• Supports HDCP Repeater Application

• Image Enhancement (White Balance and

Dithering) and Internal Pattern Generation

• EMI Minimization (SSCG and EPTO)

• Low Power Modes Minimize Power Dissipation

• Backward-Compatible Modes

2 Applications

• Automotive Display for Navigation

• Rear Seat Entertainment Systems

3 Description

The DS90UH926Q-Q1 deserializer, in conjunction

with the DS90UH925Q-Q1 serializer, provides a

solution for secure distribution of content-protected

digital video within automotive entertainment

systems. This chipset translates a parallel RGB video

interface into a single-pair high-speed serialized

interface. The digital video data is protected using the

industry standard HDCP copy protection scheme.

The serial bus scheme, FPD-Link III, supports full

duplex of high-speed forward data transmission and

low-speed backchannel communication over a single

differential link. Consolidation of video data and

control over a single differential pair reduces the

interconnect size and weight, while also eliminating

skew issues and simplifying system design.

The DS90UH926Q-Q1 deserializer has a 31-bit

parallel LVCMOS output interface to accommodate

the RGB, video control, and audio data. The device

extracts the clock from a high-speed serial stream.

An output LOCK pin provides the link status if the

incoming data stream is locked, without the use of a

training sequence or special SYNC patterns, as well

as a reference clock.

An adaptive equalizer optimizes the maximum cable

reach. EMI is minimized by output SSC generation

(SSCG) and enhanced progressive turnon (EPTO)

features.

The HDCP cipher engine is implemented in both the

serializer and deserializer. HDCP keys are stored in

on-chip memory.