1 Features

• AEC-Q100 Qualified for Automotive Applications

– Device Temperature Grade 2: –40°C to

+105°C Ambient Operating Temperature

– Device HBM ESD Classification Level 3B

– Device CDM ESD Classification Level C6

– Device MM ESD Classification Level M3

• Bidirectional Control Interface Channel Interface

With I2C-Compatible Serial Control Bus

• Supports High-Definition (720p) Digital Video

Format

• RGB888 + VS, HS, DE and Synchronized I2S

Audio Supported

• 5- to 85-MHz PCLK Supported

• Single 3.3-V Operation With 1.8-V or 3.3-V

Compatible LVCMOS I/O Interface

• AC-Coupled STP Interconnect up to 10 Meters

• Parallel LVCMOS Video Outputs

• I2C-Compatible Serial Control Bus for

Configuration

• DC-Balanced and Scrambled Data With

Embedded Clock

• Adaptive Cable Equalization

• Supports Repeater Application

• @ SPEED Link BIST Mode and LOCK Status Pin

• Image Enhancement (White Balance and

Dithering) and Internal Pattern Generation

• EMI Minimization (SSCG and EPTO)

• Low Power Modes Minimize Power Dissipation

• Backward-Compatible With FPD-Link II

2 Applications

• Automotive Display for Navigation

• Rear Seat Entertainment Systems

• Automotive Drive Assistance

• Automotive Megapixel Camera Systems

3 Description

The DS90UB926Q-Q1 deserializer, in conjunction

with the DS90UB925Q-Q1 serializer, provides a

complete digital interface for concurrent transmission

of high-speed video, audio, and control data for

automotive display and image-sensing applications.

This chipset translates a parallel RGB video interface

into a single-pair high-speed serialized interface. The

serial bus scheme, FPD-Link III, supports full duplex

of high-speed forward data transmission and lowspeed

backchannel communication over a single

differential link. Consolidation of video data and

control over a single differential pair reduces the

interconnect size and weight, while also eliminating

skew issues and simplifying system design.

The DS90UB926Q-Q1 deserializer recovers the RGB

data, three video control signals, and four

synchronized I2S audio signals. The device extracts

the clock from a high-speed serial stream. An output

LOCK pin provides the link status if the incoming data

stream is locked, without the use of a training

sequence or special SYNC patterns, as well as a

reference clock.