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DS90C383MTDXSLASHNOPB.B中文资料

厂家型号

DS90C383MTDXSLASHNOPB.B

文件大小

811.57Kbytes

页面数量

30

功能描述

DS90C383/DS90CF384 3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz

数据手册

下载地址一下载地址二到原厂下载

生产厂商

TI2

DS90C383MTDXSLASHNOPB.B数据手册规格书PDF详情

General Description

The DS90C383 transmitter converts 28 bits of LVCMOS/

LVTTL data into four LVDS (Low Voltage Differential Signaling)

data streams. A phase-locked transmit clock is transmitted

in parallel with the data streams over a fifth LVDS link.

Every cycle of the transmit clock 28 bits of input data are

sampled and transmitted. The DS90CF384 receiver converts

the LVDS data streams back into 28 bits of LVCMOS/

LVTTL data. At a transmit clock frequency of 65 MHz, 24 bits

of RGB data and 3 bits of LCD timing and control data

(FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455

Mbps per LVDS data channel. Using a 65 MHz clock, the

data throughputs is 227 Mbytes/sec. The transmitter is offered

with programmable edge data strobes for convenient

interface with a variety of graphics controllers. The transmitter

can be programmed for Rising edge strobe or Falling

edge strobe through a dedicated pin. A Rising edge transmitter

will inter-operate with a Falling edge receiver

(DS90CF384) without any translation logic. Both devices are

also offered in a 64 ball, 0.8mm fine pitch ball grid array

(FBGA) package which provides a 44 % reduction in PCB

footprint compared to the TSSOP package.

This chipset is an ideal means to solve EMI and cable size

problems associated with wide, high speed TTL interfaces.

Features

20 to 65 MHz shift clock support

Programmable transmitter (DS90C383) strobe select

Rising or Falling edge strobe)

Single 3.3V supply

Chipset (Tx + Rx) power consumption < 250 mW (typ)

Power-down mode (< 0.5 mW total)

Single pixel per clock XGA (1024x768) ready

Supports VGA, SVGA, XGA and higher addressability.

Up to 227 Megabytes/sec bandwidth

Up to 1.8 Gbps throughput

Narrow bus reduces cable size and cost

290 mV swing LVDS devices for low EMI

PLL requires no external components

Low profile 56-lead TSSOP package.

Also available in a 64 ball, 0.8mm fine pitch ball grid

array (FBGA) package

Falling edge data strobe Receiver

Compatible with TIA/EIA-644 LVDS standard

ESD rating >7 kV

Operating Temperature: −40°C to +85°C

更新时间:2025-10-28 11:01:00
供应商 型号 品牌 批号 封装 库存 备注 价格
NS/国半
23+
TSSOP56
50000
全新原装正品现货,支持订货
NS/国半
2450+
TSSOP56
6540
只做原厂原装正品现货或订货!终端工厂可以申请样品!
NS/国半
24+
TSSOP-56
60000
全新原装现货
TI(德州仪器)
24+
7350
现货供应,当天可交货!免费送样,原厂技术支持!!!
TI(德州仪器)
24+
-
690000
代理渠道/支持实单/只做原装
Rochester
25+
电联咨询
7800
公司现货,提供拆样技术支持
NS
23+
TSSOP
65480
NS
23+
TSSOP
9
现货库存
DALLAS
25+
SSOP
3600
绝对原装!现货热卖!
NS原装
12+
TSSOP-56
6000
绝对原装自己现货